/* generated configuration header file - do not edit */
#ifndef BSP_CLOCK_CFG_H_
#define BSP_CLOCK_CFG_H_
#define BSP_CFG_CLOCKS_SECURE (0)
#define BSP_CFG_CLOCKS_OVERRIDE (0)
#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */
#define BSP_CFG_HOCO_FREQUENCY (7) /* HOCO 48MHz */
#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */
#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */
#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(200,0) /* PLL Mul x200-219|Mul x200|PLL Mul x200.00 */
#define BSP_CFG_PLL_FREQUENCY_HZ (1600000000) /* PLL 1600000000Hz */
#define BSP_CFG_PLODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL1P Div /2 */
#define BSP_CFG_PLL1P_FREQUENCY_HZ (800000000) /* PLL1P 800000000Hz */
#define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL1Q Div /2 */
#define BSP_CFG_PLL1Q_FREQUENCY_HZ (800000000) /* PLL1Q 800000000Hz */
#define BSP_CFG_PLODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL1R Div /2 */
#define BSP_CFG_PLL1R_FREQUENCY_HZ (800000000) /* PLL1R 800000000Hz */
#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */
#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL2 Div /1 */
#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(48,0) /* PLL2 Mul x40-59|Mul x48|PLL2 Mul x48.00 */
#define BSP_CFG_PLL2_FREQUENCY_HZ (1152000000) /* PLL2 1152000000Hz */
#define BSP_CFG_PL2ODIVP (BSP_CLOCKS_PLL_DIV_3) /* PLL2P Div /3 */
#define BSP_CFG_PLL2P_FREQUENCY_HZ (384000000) /* PLL2P 384000000Hz */
#define BSP_CFG_PL2ODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL2Q Div /2 */
#define BSP_CFG_PLL2Q_FREQUENCY_HZ (576000000) /* PLL2Q 576000000Hz */
#define BSP_CFG_PL2ODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL2R Div /2 */
#define BSP_CFG_PLL2R_FREQUENCY_HZ (576000000) /* PLL2R 576000000Hz */
#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* Clock Src: PLL1P */
#define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */
#define BSP_CFG_CPUCLK1_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* CPUCLK1 Div /4 */
#define BSP_CFG_NPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* NPUCLK Div /2 */
#define BSP_CFG_MRICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* MRICLK Div /4 */
#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_32) /* MRPCLK Div /32 */
#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* ICLK Div /4 */
#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKA Div /8 */
#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_16) /* PCLKB Div /16 */
#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKC Div /8 */
#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKD Div /4 */
#define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKE Div /4 */
#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* BCLK Div /8 */
#define BSP_CFG_BCLKA_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2Q) /* BCLKA Src: PLL2Q */
#define BSP_CFG_BCLKA_DIV (BSP_CLOCKS_BCLKA_CLOCK_DIV_6) /* BCLKA Div /6 */
#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLK Enabled */
#define BSP_CFG_EBCLKA_SEL (0) /* EBCLK Src: BCLK (Synchronous) */
#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */
#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* CLKOUT Src: HOCO */
#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */
#define BSP_CFG_SCICLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* SCICLK Src: PLL2R */
#define BSP_CFG_SCICLK_DIV (BSP_CLOCKS_SCI_CLOCK_DIV_4) /* SCICLK Div /4 */
#define BSP_CFG_SPICLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1Q) /* SPICLK Src: PLL1Q */
#define BSP_CFG_SPICLK_DIV (BSP_CLOCKS_SPI_CLOCK_DIV_4) /* SPICLK Div /4 */
#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* CANFDCLK Src: PLL2R */
#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_10) /* CANFDCLK Div /10 */
#define BSP_CFG_GPTCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2P) /* GPTCLK Src: PLL2P */
#define BSP_CFG_GPTCLK_DIV (BSP_CLOCKS_GPT_CLOCK_DIV_4) /* GPTCLK Div /4 */
#define BSP_CFG_GPT_COUNT_CLOCK_SOURCE (0) /* GPT Src: GPTCLK */
#define BSP_CFG_LCDCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* LCDCLK Src: PLL2R */
#define BSP_CFG_LCDCLK_DIV (BSP_CLOCKS_LCD_CLOCK_DIV_4) /* LCDCLK Div /4 */
#define BSP_CFG_I3CCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2Q) /* I3CCLK Src: PLL2Q */
#define BSP_CFG_I3CCLK_DIV (BSP_CLOCKS_I3C_CLOCK_DIV_5) /* I3CCLK Div /5 */
#define BSP_CFG_UCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* USBCLK Src: PLL2R */
#define BSP_CFG_UCLK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* USBCLK Div /5 */
#define BSP_CFG_USB60CLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* USB60CLK Src: PLL2R */
#define BSP_CFG_USB60CLK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_5) /* USB60CLK Div /5 */
#define BSP_CFG_OCTACLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1Q) /* OCTACLK Src: PLL1Q */
#define BSP_CFG_OCTACLK_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_4) /* OCTACLK Div /4 */
#define BSP_CFG_ADCCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2R) /* ADCCLK Src: PLL2R */
#define BSP_CFG_ADCCLK_DIV (BSP_CLOCKS_ADC_CLOCK_DIV_4) /* ADCCLK Div /4 */
#define BSP_CFG_ESWCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* ESWCLK Src: PLL1P */
#define BSP_CFG_ESWCLK_DIV (BSP_CLOCKS_ESW_CLOCK_DIV_4) /* ESWCLK Div /4 */
#define BSP_CFG_ESWPHYCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* ESWPHYCLK Src: PLL1P */
#define BSP_CFG_ESWPHYCLK_DIV (BSP_CLOCKS_ESWPHY_CLOCK_DIV_2) /* ESWPHYCLK Div /2 */
#define BSP_CFG_ETHPHYCLK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2Q) /* ETHPHYCLK Src: PLL2Q */
#define BSP_CFG_ETHPHYCLK_DIV (BSP_CLOCKS_ETHPHY_CLOCK_DIV_32) /* ETHPHYCLK Div /32 */
#endif /* BSP_CLOCK_CFG_H_ */
